1. Field of the Invention
The present invention relates generally to semiconductor processing and, more particularly, to processing of a copper layer and subsequent layers.
2. Related Art
Integrated circuits fabricated on semiconductor substrates often require multiple levels of metal layers to provide the necessary electrical interconnections. The metal layers are separated by various insulating or dielectric layers, which are also known as inter-level dielectric (ILD) layers or inter-metal dielectric (IMD) layers. For example, in the damascene approach, a metal layer (i.e., a metal conductor pattern) is embedded in the dielectric layer or film to provide a planar interconnection layer.
Copper (Cu) can be used as the material for the metal layer. One drawback of copper is that copper atoms can migrate or diffuse into the adjacent dielectric layer, which reduces the insulator""s integrity. For example, copper diffusion in silicon oxide (Sixe2x80x94O) based dielectrics is a known problem for interconnects formed with the damascene approach.
To prevent copper diffusion, a copper diffusion barrier layer (also known as a dielectric diffusion barrier (DDB) layer) can be formed between the metal layer and the subsequently deposited dielectric layer. For example, 500 xc3x85 to 1000 xc3x85 of silicon nitride (Si3N4) or silicon carbide (SiC) can be used as a copper diffusion barrier layer. However, one drawback is that the total effective dielectric constant (k) of a damascene interconnect (i.e., an interconnect scheme formed by the damascene approach) increases due to the addition of the copper diffusion barrier layer. As is known, low-k dielectric insulators are desired to minimize resistive-capacitance (RC) interconnect delays and power consumption.
Another drawback is that the film adhesion of the copper diffusion barrier layer or dielectric layer on the copper surface is poor when copper oxide or contaminants exist. If the dielectric barrier is permeable to oxygen, copper oxide may be formed even after the planarized copper layer is capped with the dielectric layer. In addition, the presence of copper oxide on the interface of the copper layer and the dielectric barrier layer deteriorates the electron-migration performance of the copper interconnects.
Various techniques can be used to clean the copper surface to improve the film adhesion, but the copper surface may be re-oxidized, for example, if the copper diffusion barrier layer or dielectric layer contains any oxygen. Accordingly, methods are needed to improve film adhesion and reduce copper diffusion.
Systems and methods are disclosed herein, for example, to retard copper diffusion and improve film adhesion for a copper diffusion barrier layer or a dielectric etch stop layer on a copper metal layer. Two treatments within a chemical vapor deposition chamber or within sequential chambers are performed on a copper layer to clean and passivate the copper surface prior to deposition of a copper diffusion barrier layer or a dielectric etch stop layer.
The first treatment includes an in-situ plasma cleaning of the copper surface followed by the formation of an ultra-thin passivation and glue layer. The plasma cleaning contains reactive hydrogen species generated from at least one of ammonia, hydrogen, and hydrocarbon (CxHy where x=0,1,2, etc. and y=2,4,6, etc.) or their combinations. The ultra-thin passivation and glue layer is formed by performing a short initiation of an organosilane precursor or by depositing a thin silicon nitride layer. A copper diffusion barrier layer or a dielectric etch stop layer can then be formed over the cleaned and passivated copper surface using a silane or organosilane plasma with or without a carbon dioxide, a carbon monoxide, an ammonia, or a nitrogen gas feed.
For example, typical process parameters for the first treatment in a plasma enhanced chemical vapor deposition chamber include, but are not limited to, a flow rate of 2000 to 6000 sccm for ammonia, hydrogen, or hydrocarbon, a radio frequency power density of 100 to 500 W per deposition station, and a pressure of 1 to 5 Torr for a duration of 3 to 120 seconds
The typical process parameters for the second treatment in the chamber include, but are not limited to, a flow rate of 200 to 1500 sccm for tetramethylsilane (4MS) or 200 to 1000 sccm for silane (SiH4) and 2000 to 5000 sccm for nitrogen and ammonia, a radio frequency power density of 100 to 300 W, and a pressure of 1 to 5 Torr for a 1 to 5 second duration.
In accordance with one embodiment of the present invention, a method of treating a copper layer of a semiconductor device includes performing a plasma treatment on the copper layer in a chemical vapor deposition chamber followed by performing an organosilane plasma treatment or thin silicon nitride deposition in the same or sequential chemical vapor deposition chamber to passivate and glue the copper layer. The method may further include depositing a copper diffusion barrier layer after the organosilane plasma treatment has been performed.
In accordance with another embodiment of the present invention, a method of semiconductor processing includes introducing an ammonia gas, a hydrogen gas, a hydrocarbon gas, or one or more of their combinations, into a chemical vapor deposition chamber to remove surface oxide and contaminants on a copper layer of a semiconductor device and introducing an organosilane gas or silane and nitrogen gases into the same or sequential chemical vapor deposition chamber to prevent oxidation of the copper layer after the copper layer is cleaned. The method may further include introducing an organosilane or silane gas, with or without a carbon dioxide, a carbon monoxide, an ammonia, and/or a nitrogen gas, into the same or sequential chemical vapor deposition chamber to deposit a copper diffusion barrier layer or etch stop layer.
A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.